One crucial point in wafer-level integrated circuit (IC) manufacturing is the deconstruction of these structures by reverse engineering (RE). The aim is to conduct verification, failure analysis, research and development of the internal structures of those devices. The RE process comprises four main steps:
- decapsulation, which means exposure of internal components of the chip to examine dies, interconnections and other features
- delayering including a destructive layer-by-layer analysis of the die to see each metal layer, passivation layer, polysilicon layer and active layer
- imaging, typically realized by SEM, TEM or SCM
- postprocessing with functional analysis and identification of chip
Why ion beam etching?
As modern chip design pushes for smaller, more powerful and more compact devices, the requirements for a precise and uniform delayering (sequential removing) becomes even stricter. The dimensions of the chip shrink to a level where established techniques like wet chemical etching, chemical mechanical polishing (CMP) and dry plasma etching become disproportionally costly, error prone and limited in its utilization. Modern reversed engineering requires delayering with highest accuracy within the µm, nm and atomic level thickness range for different materials at once.
To meet the strict requirements ion beam etching can be used for the removing process. This process applies a chemically and physically active ion bombardment by a mixture of inert and reactive ions and thereby allows to remove all materials that face the ion beam.
By selecting a certain gas composition as well as changing the angle of incidence the etch rate selectivity between different materials can be adjusted. This and the possibility to precisely tune the ion beam density and ion beam energy can influence critical material removal parameters like etch rate, material selectivity and removal uniformity to finally produce a flat, uniform surface at the required scale.
Furthermore, processing with a helium backside wafer cooling keeps the substrate temperature low and prevent any damage of temperature sensitive structures. Additionally, operation with optical emission spectroscopy (OES) or secondary ion mass spectrometry (SIMS) end point detection systems allows to precisely measure the nature of the sputtered material and thus an exact definition of etch stops is possible (before, after or within a certain layer). The detection systems are sensitive enough for etching of sub-nm thin layers.
Example: Delayering of an IC chip device
A typical delayering procedure for a die can be seen in the figures 2 and 3. Figure 2 indicates the etch stops where the delayering should stop for imaging and evaluating the structures of the corresponding layer. The etching process was recorded using an optical emission spectrometer (OES), see figure 3. The spectral lines belonging to Cu were identified and recorded as a trend line. End points were set at the minima of the Cu trend lines in order to analyze each layer by SEM. Each individual Cu layer is distinguishable in every peak OES signal.
In contrast to prevailing delayering techniques the nature of ion beam etching prevents invasive side effects that distort layers or interfere with the integrity of subsequent measurements. In addition, the process avoids residual contaminations, layer damaging, layer corrosion, percolation of fluids to lower layers, and exposure to heat and radiation, which might influence the nature of the surface materials from its native state. This makes ion beam etching the method of choice for low damage, high resolution and high uniformity delayering for reverse engineering.
Related Products - scia Mill 150 & scia Mill 200
- Etching with inert gases to avoid after-corrosion
- Helium cooling of substrates for use of photoresist
- Reactive gas compatibility in RIBE and CAIBE processing
- Ion beam source with high stability, adjustable ion energy and ion current density
- In-situ measurement for exact end point detection with SIMS or OES
- Complete software integration and automated processes via recipe